1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device. More particularly, the present invention relates to a method of fabricating a transistor having a triple channel in a memory device.
2. Description of the Prior Art
Recently, as semiconductor devices have been highly integrated, channel lengths and channel widths of a transistor are significantly shortened. As the semiconductor devices are equipped with a short channel structure, the threshold voltage exerts a serious influence on the channel width. Accordingly, the conventional two-dimensional planar channel structure presents limitations to obtain the target threshold voltage of the transistor required for a specific semiconductor device.
In order to solve the above problem, studies and researches have been actively performed in relation to a three-dimensional transistor for applications in a logic device. In particular, a fin transistor having a triple channel feature has been recently spotlighted as potentially the next-generation nano scale transistor.
Since three surfaces of the triple channel structure of the fin transistor are used as channels, the fin transistor provides the superior ON-OFF characteristics and the superior current drivability, while lowering the back bias dependency of the threshold voltage. For this reason, studies and researches for applying the fin transistor to the logic device have been actively carried out.
FIGS. 1A to 1E are drawn to illustrate the procedure for fabricating a conventional fin transistor.
As shown in FIG. 1A, a trench is formed in an isolation layer of a semiconductor substrate 1 in such a manner that an active area 1a vertically protrudes from a predetermined portion of the semiconductor substrate 1. In addition, a field oxide layer 2 is formed in the trench.
Then, as shown in FIG. 1B, the field oxide layer 2 is etched by a predetermined thickness through a wet etching process and a dry etching process, thereby exposing the sides of the upper portion of the active area 1a. 
After that, as shown in FIG. 1C, a gate insulation layer 3 is formed on the exposed upper portion of the active area 1a. 
Then, as shown in FIG. 1D, a first conductive layer 4a of polysilicon and a second conductive layer 4b of a low-resistant material are sequentially deposited on the gate insulation layer 3 and the field oxide layer 2. The second conductive layer 4b includes WSix or W.
After that, as shown in FIG. 1E, predetermined portions of the first and second conductive layers 4a and 4b are sequentially etched, thereby forming a low-resistant gate electrode 4 having a stacked structure of the first and second conductive layers 4a and 4b and extending across the gate insulation layer 3 on the upper portion of the active area 1a while overlapping the channel area. Herein, reference characters S and D represent a source area and a drain area of the fin transistor, respectively.
However, if the fin transistor is fabricated by the above processes, a void V as shown in FIG. 1E may be formed in an “I” section of the low-resistant gate electrode 4 when forming the second conductive layer 4b, because a step difference in height is present between the field oxide layer 2 and the active area 1a that vertically protrudes above the field oxide layer 2. All of these factors contribute to undesirable increase of resistance of the low-resistant gate electrode 4.
To solve the above problem, another conventional fin transistor has been suggested. FIGS. 2A to 2G illustrate a procedure for fabricating another conventional fin transistor.
As shown in FIG. 2A, a trench is formed in an isolation layer of a semiconductor substrate 1 in such a manner that an active area 1a vertically protrudes from a predetermined portion of the semiconductor substrate 1. In addition, a field oxide layer 2 is formed in the trench.
Then, as shown in FIG. 2B, the field oxide layer 2 is etched by a predetermined thickness through a wet etching process and a dry etching process, thereby exposing the sides of the upper portion of the active area 1a. 
After that, as shown in FIG. 2C, a gate insulation layer 3 is formed on the exposed upper portion of the active area 1a. 
Then, as shown in FIG. 2D, a first conductive layer 4a of polysilicon is deposited on the gate insulation layer 3 and the field oxide layer 2.
Thereafter, as shown in FIG. 2E, the first conductive layer 4a is planarized through a chemical mechanical polishing (CMP) process. As a result, the first conductive layer 4a would have the thickness of “t1” for the portion above the active area 1a and the thickness of “t1+α” for the portion above the field oxide layer 2. Because the first conductive layer 4a is planarized, the step difference existing between the active area 1a and the field oxide layer 2 can be disregarded. Therefore, formation of a void on the layers that are subsequently deposited on the planarized first conductive layer 4a (for example, a process for depositing a second conductive layer 4b as shown in FIG. 2F) is prevented.
As shown in FIG. 2F, the second conductive layer 4b made from a low-resistant material is deposited on the planarized first conductive layer 4a. The material for the second conductive layer 4b includes WSix or W.
After that, as shown in FIG. 2G, predetermined portions of the first and second conductive layers 4a and 4b are sequentially etched, thereby forming a low-resistant gate electrode 4 having a stacked structure of the first and second conductive layers 4a and 4b and extending across the gate insulation layer 3 on the upper portion of the active area 1a while overlapping the channel area. Herein, reference characters S and D represent a source area and a drain area of the fin transistor, respectively.
If the low-resistant gate electrode 4 is fabricated by depositing an upper layer on a lower layer planarized by the CMP process, it is possible to prevent a void being created in the low-resistant gate electrode 4, but it presents other process problems. That is, since the thickness (t1+α) of the first conductive layer 4a on the field oxide layer 2 is relatively larger than the thickness (t1) of the first conductive layer 4a on the active area 1a, the process for fabricating the low-resistant gate electrode 4 by etching the first and second conductive layers 4a and 4b is difficult, and would lead to lowering of the yield rate of the transistor.